module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);

    `define STT_W 6
    `define STT_W1 `STT_W - 1

    wire [`STT_W1:0]   state = y;
    reg [`STT_W1:0]   nxt_state;

    localparam sA  = `STT_W'd1;
    localparam sB  = `STT_W'd2;
    localparam sC  = `STT_W'd4;
    localparam sD  = `STT_W'd8;
    localparam sE  = `STT_W'd10;
    localparam sF  = `STT_W'd20;

    // State transition logic (combinational)
    always @(*) begin
        nxt_state[0]    <=  w ? state[0] || state[3] : 1'b0;
        nxt_state[1]    <=  w ? 1'b0 : state[0];
        nxt_state[2]    <=  w ? 1'b0 : state[5] || state[1];
        nxt_state[3]    <=  w ? state[1] || state[2] || state[4] || state[5]: 1'b0;
        nxt_state[4]    <=  w ? 1'b0 : state[4] || state[2];
        nxt_state[5]    <=  w ? 1'b0 : state[3];
    end
 
    assign  Y2   =   nxt_state[1];
    assign  Y4   =   nxt_state[3];

endmodule
